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Virtual Event
June 2
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Wednesday, June 2
 

16:00 CEST

RISC-V Welcome - Kim McMahon, RISC-V International

16:05 CEST

RISC-V Tools & Runtime HSC Overview - Christoph Müllner, SBA Research & Philipp Tomsich, VRULL GmbH

16:15 CEST

Java on RISC-V: OpenJDK Porting Work Update - Sanhong Li & Kevin Kuai, Alibaba Cloud

16:35 CEST

Analysis for Code Size Opportunities in RISC V - Ibrahim Abu Kharmeh, Huawei UK

17:05 CEST

Programmer Productivity and Performance on Embedded RISC-V CPUs - Nick Brown, EPCC at the University of Edinburgh

17:15 CEST

CFU Playground: Model-specific Acceleration on FPGAs - Timothy Callahan & Alan V. Green,Google

17:45 CEST

Linker Relaxation in LLD - Chih-Mao Chen, Andes Technology

18:05 CEST

Exploring Static Code Generation and SIMD-Acceleration for Machine Learning on RISC-V - Rafael Stahl, Technical University of Munich

18:25 CEST

Porting and Optimization V8 for RISC-V - Ji Qiu, Institute of Software, Chinese Academy of Sciences

18:35 CEST

Panel: Toolchains & Runtime - Philipp Tomsich, Vrull; Christoph Müllner, SBA Research; Kito Cheng & Evandro Menezes, SiFive; Jessica Clarke, University of Cambridge; John Leidel, Tactical Computing Laboratorie...
 
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