RISC-V Forum: Developer Tools & Tool Chains

Many applications in Alibaba are written in Java with a billion lines of code. Alibaba's investment in OpenJDK dated back to 2010. Alibaba Dragonwell, is a downstream of OpenJDK, and customized to meet the needs of rapidly growing business of the Alibaba ecosystem.  RISC-V, as an open source architecture, is the new exciting area in computer architecture and is gaining more attractions.   By collaborating with communities, we are investigating the port work of OpenJDK on RISC-V. In this talk, we will describe the current status of port development on OpenJDK for RISC-V architecture, and the combability and performance issues while running the full Java application on RISC-V with OpenJDK.   The suggested agenda is as follows: -    Introduction to the Alibaba Java usage on RISC-V -    Current status of JDK port work -    Evaluation of popular java frameworks on RISC-V with OpenJDK -    Performance optimization for SPECjbb2015 -    Comparison between RISC-V and ARM  We still see the gap between the current work and the final version ready for productions. While the experience we learned during porting process could be useful to the community.  

Zce is a RISC-V extension currently being designed to aid RISC-V to compete with alternative ISAs in term of code size density. For the extension to be effective, one would need to find possible optimisation opportunities, and effectively and accurately estimate code size savings from such optimisations and also estimate if such optimisations would present any performance penalty. In this talk, Ibrahim will shortly go over why code size density is important, introduce the Zce extension and its main proposed instructions. Then he will introduce the analysis script used to estimate projected code savings, discuss how it works and its limitation. Finally, he will conclude with projected code size savings from the extension proposed instructions.

An already popular target for RISC-V, which will likely grow further in future, is low power, low-cost embedded workloads. But these CPUs are typically running bare-metal with tiny amounts of directly connected memory and significant penalties in accessing larger memory spaces further away, if indeed such memory spaces are available. Consequently they are difficult and time consuming to program.  We aim to democratise the programming of such embedded RISC-V CPUs, enabling a more diverse set of programmers to exploit them, and fast prototyping, via Python. In such architectures memory is everything, and our Python interpreter is approximately 24KB making it the smallest in the world. However, there are inevitable performance limitations associated with interpreters and therefore we developed our Olympus compiler. Using a novel dynamic loading technique under the hood, this results in the ability to run unlimited Python code sizes with approximately 10KB of memory, at close to native performance. These compilation techniques are also applicable to a wider set of dynamic languages on RISC-V.  The research associated with ePython has been highly successful, and we are now looking to productionise this enabling potential users to download and use our work. In this lightening talk we will provide a brief overview of ePython for RISC-V, describe how the internals support such constrained architectures, and share our roadmap for productionisation of this open-source technology.

This talk describes the CFU Playground, an open-source framework that an engineer, intern, or student can use to design and evaluate enhancements to an FPGA-based soft RISC-V processor, specifically to increase the performance of machine learning (ML) tasks through the addition of custom function units (CFUs). The goal is to abstract away most infrastructure details so that the user can get up to speed quickly and focus solely on adding new processor functions, exploiting them in the computation, and measuring the results.  The presentation describes the process of identifying hot spots in the code during an inference using a specific model, constructing a CFU to support new custom instructions, modifying the TensorFlow Lite kernel library to use these new instructions, measuring the results, and iterating.  The goal is not to design a general ML accelerator; the goal is to jointly specialize the processor and ML kernels just for the model of interest.  All IP and software used is open sourced and licensed permissively -- the open RISC-V ISA that allows new custom instructions, the VexRiscv soft core implementation, the LiteX system-on-chip IP, the Symbiflow FPGA toolchain, Renode and Verilator simulators, and TensorFlow Lite kernel libraries.  Thus, the combined CPU, CFU, and kernel libraries that the user develops are not tied to any particular FPGA vendor; there are no licensing restrictions or fees; and there is no dependence on any black box proprietary tools.

The deployment of machine learning applications on microcontrollers known as TinyML enables new low-power applications and always-on devices. The RISC-V architecture is attractive for such microcontrollers, because it provides easy extensibility, a healthy ecosystem and no license costs. The major challenges with resource-constrained devices are run time and memory usage. Existing machine learning frameworks provide runtime libraries that dynamically load and execute a model, but this entails overheads. In this talk, two static code generators based on TensorFlow Lite for Microcontrollers and TVM are presented, that avoid these overheads by generating static code to execute the model. Additionally, machine learning kernel implementations based on a RISC-V version of CMSIS-NN are provided that make use of the RISC-V P- and V-Extensions to accelerate inner loops with SIMD-Operations. The contributions were evaluated on the TinyMLPerf benchmark with the ETISS simulator and show the benefits of static code generation and specialized kernel implementations.

V8 is the JavasSript and WebAssembly engine of the Google's Chromium project. The Chrome browser, which has the largest market share in the world, bases on it. From the beginning of the last year, we PLCT V8 team has been devoted to the porting of V8 for RV64G instruction set. Until now, by working together with RIOS lab and Futurewei, we finished porting, upstreaming and made RISC-V V8 functionally stable. We also started carrying out performance evaluation and optimization for it. It's expected that RISC-V will become a tier-1 platform for V8 and have competitive performance comparing to the other main stream ISA at the end of this year.