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June 2
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Wednesday, June 2
 

16:00 CEST

RISC-V Welcome - Kim McMahon, RISC-V International
Speakers
avatar for Kim McMahon

Kim McMahon

Director of Marketing, RISC-V International
Kim McMahon is the Director of Marketing of RISC-V International. She comes to RISC-V with a deep background in marketing for open source and technology. She has spent her career with companies such as SGI, Cray, VMware, and the {code} Team at Dell, where she honed her love for HPC... Read More →


Wednesday June 2, 2021 16:00 - 16:05 CEST

16:05 CEST

RISC-V Tools & Runtime HSC Overview - Christoph Müllner, SBA Research & Philipp Tomsich, VRULL GmbH
Speakers
avatar for Christoph Müllner

Christoph Müllner

Software developer and security researcher, SBA Research
Christoph Müllner is a Software Developer and IT Security Researcher at SBA Research.He has been working on compilers, managed runtimes and embedded systems for more than 13 years.His experience includes static and dynamic program analysis, profiling, benchmarking, porting, and optimizing... Read More →
avatar for Philipp Tomsich

Philipp Tomsich

Chief Technologist, VRULL GmbH
Dr. Philipp Tomsich is the Founder and Chief Technologist of VRULL GmbH, an engineering consultancy focused on engineering performance solutions through compiler optimizations, runtime performance tuning, system-level optimization, and hard-/software co-engineering on the architectural and micro-architectural level.  He supports the RISC-V mission as... Read More →



Wednesday June 2, 2021 16:05 - 16:15 CEST

16:15 CEST

Java on RISC-V: OpenJDK Porting Work Update - Sanhong Li & Kevin Kuai, Alibaba Cloud
Many applications in Alibaba are written in Java with a billion lines of code. Alibaba's investment in OpenJDK dated back to 2010. Alibaba Dragonwell, is a downstream of OpenJDK, and customized to meet the needs of rapidly growing business of the Alibaba ecosystem.  RISC-V, as an open source architecture, is the new exciting area in computer architecture and is gaining more attractions.   By collaborating with communities, we are investigating the port work of OpenJDK on RISC-V. In this talk, we will describe the current status of port development on OpenJDK for RISC-V architecture, and the combability and performance issues while running the full Java application on RISC-V with OpenJDK.   The suggested agenda is as follows: -    Introduction to the Alibaba Java usage on RISC-V -    Current status of JDK port work -    Evaluation of popular java frameworks on RISC-V with OpenJDK -    Performance optimization for SPECjbb2015 -    Comparison between RISC-V and ARM  We still see the gap between the current work and the final version ready for productions. While the experience we learned during porting process could be useful to the community.  

Speakers
avatar for Sanhong Li

Sanhong Li

Director of Compiler & Runtime, Alibaba Cloud
Sanhong Li has been working on Java since 2004, where he began at Intel R&D Lab, implementing JSR135. He progressed to working on developing IBM's J9VM in 2010, where he led a project to develop multi-tenancy technology for the JVM. In 2014, he joined Alibaba to lead the development... Read More →
KK

Kevin Kuai

JVM architect, Alibaba Cloud
Kevin Wei has been working on the Just-in-Time compiler of HotSpot JVM as a principal engineer in HPE since 2007. In 2018, He joined Alibaba Cloud as a JVM architect, leading the Java compiler team to improve the Java performance of various workloads in the cloud.



Wednesday June 2, 2021 16:15 - 16:35 CEST
  Session
  • Slides Included Yes

16:35 CEST

Analysis for Code Size Opportunities in RISC V - Ibrahim Abu Kharmeh, Huawei UK
Zce is a RISC-V extension currently being designed to aid RISC-V to compete with alternative ISAs in term of code size density. For the extension to be effective, one would need to find possible optimisation opportunities, and effectively and accurately estimate code size savings from such optimisations and also estimate if such optimisations would present any performance penalty. In this talk, Ibrahim will shortly go over why code size density is important, introduce the Zce extension and its main proposed instructions. Then he will introduce the analysis script used to estimate projected code savings, discuss how it works and its limitation. Finally, he will conclude with projected code size savings from the extension proposed instructions.

Speakers
IA

Ibrahim Abu Kharmeh

CPU Engineer, Huawei UK
Ibrahim has recently completed an Electronic Engineering MSc (Micro Electronics Stream)at the University of Southampton. During his masters degree, he researched the feasibility of implementing a NISC based processor for signal processing. He is currently working for Huawei Bristol... Read More →



Wednesday June 2, 2021 16:35 - 17:05 CEST
  Session
  • Slides Included Yes

17:05 CEST

Programmer Productivity and Performance on Embedded RISC-V CPUs - Nick Brown, EPCC at the University of Edinburgh
An already popular target for RISC-V, which will likely grow further in future, is low power, low-cost embedded workloads. But these CPUs are typically running bare-metal with tiny amounts of directly connected memory and significant penalties in accessing larger memory spaces further away, if indeed such memory spaces are available. Consequently they are difficult and time consuming to program.  We aim to democratise the programming of such embedded RISC-V CPUs, enabling a more diverse set of programmers to exploit them, and fast prototyping, via Python. In such architectures memory is everything, and our Python interpreter is approximately 24KB making it the smallest in the world. However, there are inevitable performance limitations associated with interpreters and therefore we developed our Olympus compiler. Using a novel dynamic loading technique under the hood, this results in the ability to run unlimited Python code sizes with approximately 10KB of memory, at close to native performance. These compilation techniques are also applicable to a wider set of dynamic languages on RISC-V.  The research associated with ePython has been highly successful, and we are now looking to productionise this enabling potential users to download and use our work. In this lightening talk we will provide a brief overview of ePython for RISC-V, describe how the internals support such constrained architectures, and share our roadmap for productionisation of this open-source technology.

Speakers
avatar for Nick Brown

Nick Brown

Research Fellow, EPCC at the University of Edinburgh



Wednesday June 2, 2021 17:05 - 17:15 CEST
  Session
  • Slides Included Yes

17:15 CEST

CFU Playground: Model-specific Acceleration on FPGAs - Timothy Callahan & Alan V. Green,Google
This talk describes the CFU Playground, an open-source framework that an engineer, intern, or student can use to design and evaluate enhancements to an FPGA-based soft RISC-V processor, specifically to increase the performance of machine learning (ML) tasks through the addition of custom function units (CFUs). The goal is to abstract away most infrastructure details so that the user can get up to speed quickly and focus solely on adding new processor functions, exploiting them in the computation, and measuring the results.  The presentation describes the process of identifying hot spots in the code during an inference using a specific model, constructing a CFU to support new custom instructions, modifying the TensorFlow Lite kernel library to use these new instructions, measuring the results, and iterating.  The goal is not to design a general ML accelerator; the goal is to jointly specialize the processor and ML kernels just for the model of interest.  All IP and software used is open sourced and licensed permissively -- the open RISC-V ISA that allows new custom instructions, the VexRiscv soft core implementation, the LiteX system-on-chip IP, the Symbiflow FPGA toolchain, Renode and Verilator simulators, and TensorFlow Lite kernel libraries.  Thus, the combined CPU, CFU, and kernel libraries that the user develops are not tied to any particular FPGA vendor; there are no licensing restrictions or fees; and there is no dependence on any black box proprietary tools.

Speakers
avatar for Timothy Callahan

Timothy Callahan

Software Engineer, Google
Tim Callahan studied electrical engineering at the University of Minnesota, computer science at the University of Cambridge, and attained graduate degrees at UC Berkeley, also in computer science. His graduate research and much of his career centered around compiling from various... Read More →
AV

Alan V. Green

Staff Software Engineer, Google
Alan is a Staff Software Engineer on the Google ChromeOS Platform team. He works on both making existing ML acceleration hardware accessible to the ChromeOS and on projects that require new hardware ML accelerators. Alan also contributes to the CFU-Playground project, exploring software... Read More →



Wednesday June 2, 2021 17:15 - 17:45 CEST
  Session
  • Slides Included Yes

17:45 CEST

Linker Relaxation in LLD - Chih-Mao Chen, Andes Technology
Linker relaxation is an important link-time optimization in RISC-V. By marking code sequences with relaxation hints and rewriting them with shorter ones at link time when the final addresses are known, the linker can create smaller and more efficient programs. However such optimization isn't available in LLD (LLVM's linker), leading to larger programs and compatibility issues with other toolchains that assume relaxation.

This talk will provide a brief overview on how linker relaxation works in RISC-V, describe our relaxation implementation and alignment handling in LLD, and present benchmarking results after enabling relaxation.

Speakers
CC

Chih-Mao Chen

Toolchain Engineer, Andes Technology
Chih-Mao Chen is a software developer at Andes Technology, where he is responsible at developing RISC-V toolchain based on the LLVM compiler infrastructure.


Wednesday June 2, 2021 17:45 - 18:05 CEST

18:05 CEST

Exploring Static Code Generation and SIMD-Acceleration for Machine Learning on RISC-V - Rafael Stahl, Technical University of Munich
The deployment of machine learning applications on microcontrollers known as TinyML enables new low-power applications and always-on devices. The RISC-V architecture is attractive for such microcontrollers, because it provides easy extensibility, a healthy ecosystem and no license costs. The major challenges with resource-constrained devices are run time and memory usage. Existing machine learning frameworks provide runtime libraries that dynamically load and execute a model, but this entails overheads. In this talk, two static code generators based on TensorFlow Lite for Microcontrollers and TVM are presented, that avoid these overheads by generating static code to execute the model. Additionally, machine learning kernel implementations based on a RISC-V version of CMSIS-NN are provided that make use of the RISC-V P- and V-Extensions to accelerate inner loops with SIMD-Operations. The contributions were evaluated on the TinyMLPerf benchmark with the ETISS simulator and show the benefits of static code generation and specialized kernel implementations.

Speakers
RS

Rafael Stahl

Doctoral Candidate, Technical University of Munich
Rafael Stahl is a doctoral candidate at the Technical University of Munich at the Chair of Electronic Design Automation in his fourth year. He received his Bachelor and Master in "Electrical Engineering and Information Technology" from TU Munich. He gathered work experience at the... Read More →



Wednesday June 2, 2021 18:05 - 18:25 CEST
  Session
  • Slides Included Yes

18:25 CEST

Porting and Optimization V8 for RISC-V - Ji Qiu, Institute of Software, Chinese Academy of Sciences
V8 is the JavasSript and WebAssembly engine of the Google's Chromium project. The Chrome browser, which has the largest market share in the world, bases on it. From the beginning of the last year, we PLCT V8 team has been devoted to the porting of V8 for RV64G instruction set. Until now, by working together with RIOS lab and Futurewei, we finished porting, upstreaming and made RISC-V V8 functionally stable. We also started carrying out performance evaluation and optimization for it. It's expected that RISC-V will become a tier-1 platform for V8 and have competitive performance comparing to the other main stream ISA at the end of this year.

Speakers
avatar for Ji Qiu

Ji Qiu

Software Engineer and Project Manager, Institute of Software, Chinese Academy of Sciences
Ji Qiu is a software engineer and project manager at the Institute of Software, Chinese Academy of Sciences. She worked as the leader of the compiler team at the Spreadtrum Communications (from 2015 to 2018) and the Loongson Technology (from 2013 to 2015). She finished her Ph.D study... Read More →



Wednesday June 2, 2021 18:25 - 18:35 CEST
  Session
  • Slides Included Yes

18:35 CEST

Panel: Toolchains & Runtime - Philipp Tomsich, Vrull; Christoph Müllner, SBA Research; Kito Cheng & Evandro Menezes, SiFive; Jessica Clarke, University of Cambridge; John Leidel, Tactical Computing Laboratories
Speakers
JL

John Leidel

Chief Scientist, Tactical Computing Laboratories
John Leidel is the founder and Chief Scientist of Tactical Computing Laboratories where he leads efforts in programming model, compiler and algorithm research for advanced computing architectures.  He is also an adjunct researcher in the Data Intensive Scalable Computing Laboratory... Read More →
avatar for Philipp Tomsich

Philipp Tomsich

Chief Technologist, VRULL GmbH
Dr. Philipp Tomsich is the Founder and Chief Technologist of VRULL GmbH, an engineering consultancy focused on engineering performance solutions through compiler optimizations, runtime performance tuning, system-level optimization, and hard-/software co-engineering on the architectural and micro-architectural level.  He supports the RISC-V mission as... Read More →
avatar for Christoph Müllner

Christoph Müllner

Software developer and security researcher, SBA Research
Christoph Müllner is a Software Developer and IT Security Researcher at SBA Research.He has been working on compilers, managed runtimes and embedded systems for more than 13 years.His experience includes static and dynamic program analysis, profiling, benchmarking, porting, and optimizing... Read More →
avatar for Kito Cheng

Kito Cheng

Compiler Engineer, SiFive
avatar for Evandro Menezes

Evandro Menezes

Compiler Engineer, SiFive
Compiler engineer with contributions to GCC for x86-64, Hexagon and AArch64 and to LLVM for Hexagon, AArch64 and RISC-V. Having begun venturing in toolchain development after a career in embedded systems writing real time applications and kernels when AMD led the transition of the... Read More →
JC

Jessica Clarke

PhD Student, University of Cambridge


Wednesday June 2, 2021 18:35 - 19:15 CEST
 
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