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June 2
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Wednesday, June 2 • 17:05 - 17:15
Programmer Productivity and Performance on Embedded RISC-V CPUs - Nick Brown, EPCC at the University of Edinburgh

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An already popular target for RISC-V, which will likely grow further in future, is low power, low-cost embedded workloads. But these CPUs are typically running bare-metal with tiny amounts of directly connected memory and significant penalties in accessing larger memory spaces further away, if indeed such memory spaces are available. Consequently they are difficult and time consuming to program.  We aim to democratise the programming of such embedded RISC-V CPUs, enabling a more diverse set of programmers to exploit them, and fast prototyping, via Python. In such architectures memory is everything, and our Python interpreter is approximately 24KB making it the smallest in the world. However, there are inevitable performance limitations associated with interpreters and therefore we developed our Olympus compiler. Using a novel dynamic loading technique under the hood, this results in the ability to run unlimited Python code sizes with approximately 10KB of memory, at close to native performance. These compilation techniques are also applicable to a wider set of dynamic languages on RISC-V.  The research associated with ePython has been highly successful, and we are now looking to productionise this enabling potential users to download and use our work. In this lightening talk we will provide a brief overview of ePython for RISC-V, describe how the internals support such constrained architectures, and share our roadmap for productionisation of this open-source technology.

Speakers
avatar for Nick Brown

Nick Brown

Research Fellow, EPCC at the University of Edinburgh



Wednesday June 2, 2021 17:05 - 17:15 CEST
  Session
  • Slides Included Yes